1. Field of Invention
The present invention relates to a voltage level shifting apparatus. More particularly, the present invention relates to a voltage level shifting apparatus capable of operating in either a high-voltage mode or a low-voltage mode.
2. Description of Related Art
Please refer to FIG.1, which is a circuit diagram of a conventional voltage level shifting apparatus 100. The voltage level shifting apparatus 100 has the transistors P1 and P2 which are cross-coupled to form a cross-coupled transistor pair. The gate of the transistor P1 is coupled to a node IN2, and the gate of the transistor P2 is coupled to a node IN1. The sources/drains of the transistors P1 and P2 receive an operational voltage VPP. Moreover, the voltage level shifting apparatus 100 further comprises a transistor pair composed of transistors P3 and P4, a transistor pair composed of transistors N1 and N2, and a transistor pair composed of transistors N3 and N4.
The gates of the transistors P3 and P4 receive a reference voltage IV. The transistor P3 is serially coupled between the sources/drains of the transistors P1 and N1, and the transistor P4 is serially coupled between the sources/drains of the transistors P2 and N2. The gates of the transistors N1 and N2 receive a logic operational voltage Vdd. The transistor N1 is coupled between the transistors N3 and P3, and the transistor N2 is coupled between the transistors N4 and P4. The transistor N3 is coupled between the transistor N1 and a ground voltage GND, and the transistor N4 is coupled between the transistor N2 and the ground voltage GND.
When the operational voltage VPP is greater than the logic operational voltage Vdd, the voltage level shifting apparatus 100 raises the voltage levels of the input voltages IN and INB to generate and output the output voltages VOUT and VOUTB. The original voltage levels of the input voltages IN and INB are not greater than the logic operational voltage Vdd, and the maximum voltage levels of the output voltages VOUT and VOUTB could be equal to the operational voltage VPP. Since the operational voltage VPP could be transmitted to the transistors N1 and N2 through the transistors P3 and P4, and the logic operational voltage Vdd applied to the gates of the transistors N1 and N2 is less than the operational voltage VPP applied to the gates of the transistors P1 and P2, the transistors N1 and N2 of the voltage level shifting apparatus 100 must be laterally diffused metal oxide semiconductor (LDMOS) transistors, which are capable of withstanding a high cross-voltage (i.e. a voltage greater than the logic operational voltage Vdd).
Moreover, the voltage level shifting apparatus 100 further comprises a transistor string composed of transistors N5 and N7 and a transistor string composed of transistors N6 and N8. The transistors N5 and N6 are LDMOS transistors, which should be capable of withstanding high cross-voltages. The two transistor strings (N5 and N7) and (N6 and N8) are used to support the voltage level shifting apparatus 100 to perform an operation of shifting the voltage levels of the input voltages IN and INB when the operational voltage VPP is a low voltage.
For embedded memory design based on the standard CMOS logic process, there is strict constraint imposing on the bias applied to the device terminals To be specific, if the logic operational voltage is defined to be Vdd, the bias difference should not exceed the logic operational voltage Vdd for any of the drain, source, gate, and bulk terminals. If the bias difference does exceed the criteria, the imposed bias will damage the device reliability and the circuit will be worn out with time. Therefore, for a level shifting apparatus manufactured by the standard COM logic process, if the operational voltage VPP exceeds the logic operational voltage Vdd, the terminal bias difference of each device of the level shifting apparatus should be carefully examined. In the field of embedded nonvolatile memory design, the operational voltage VPP relates to the high voltage write power supply and may easily exceed as much as three times of the logic operational voltage Vdd. Accordingly, terminal bias difference across each device of the level shifting apparatus should be examined even more thoroughly to avoid the reliability issue.
In other words, the conventional voltage level shifting apparatus 100 fails to obey the terminal bias difference constraint mentioned above for logic device. For example, if the operational voltage VPP is set to be three times of the logic operational voltage Vdd (i.e. 3×Vdd) and the level shifting apparatus 100 operates in a state where the input voltage IN is equal to logic operational voltage Vdd and the input voltage INB is equal to a second logic operational voltage Vss (e.g. the ground voltage GND). As a result, the output voltage VOUTB is equal to the second logic operational voltage Vss, and the output voltage VOUT is equal to the operational voltage VPP. Then the aforementioned stress bias will be imposed on the transistors P3 and P4. On the one hand, even if the reference voltage IV is equal to two times of the logic operational voltage Vdd (i.e. 2×Vdd) to relieve the constraint of the source-gate bias difference for both the transistors P3 and P4, because the node IN2 (i.e. bulk bias for the transistor P4) is biased to (IV+|VTP|), where VTP is the threshold voltage of the transistor P4, the gate-drain bias difference of the transistor P4 is equal to (2×Vdd−Vss), which exceeds the maximum-allowed value of Vdd. And, the source-drain bias difference of the transistor P4 is equal to (2×Vdd+|VTP|−Vss), which still exceeds the maximum-allowed value of Vdd. On the other hand, a similar stress bias condition occurs when the level shifting apparatus 100 operates in another state where IN=Vss and INB=Vdd. Obviously, in this state, the transistor P3 will experience either (2×Vdd−Vss) or (2×Vdd+|VTP|−Vss) stress bias condition. In brief, to solve the issue to relieve terminal stress bias condition of the standard CMOS logic device having an embedded nonvolatile memory and operating in a high voltage (e.g. as high as 3 times of the logic operational voltage Vdd), a new level shifting apparatus is proposed in the present invention.